Publication Type:

Conference Paper


2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, Trivandrum, Kerala, p.157-162 (2011)





3D topology, Algorithms, Computational complexity, delay, drop probability, Drops, Electric network topology, Electronic data interchange, Energy dissipation, latency, Microprocessor chips, Network routing, NoC, Programmable logic controllers, Routers, routing, Routing algorithms, SoC, switch buffer size, Three dimensional, Topology, VLSI circuits


In the nano scaled transistors integration era, interconnection of IP blocks and data exchange among the IP blocks are crucial concerns in System on Chip (SoC). Network-on-Chip (NoC) is an on-chip communication methodology proposed to resolve the increased interconnection problems in SoC. In deep sub-micron regime, 3D NoC becomes an emerging research area in recent years as the three dimensional (3D) integrated circuits (ICs) can offer shorter interconnection wire and dissipate lesser power. Major area of the 3D NoC research is network topology and routing techniques. In this paper, we present an NS-2 (Network Simulator) simulation environment for two 3D network topologies (GBT and CBT) and cluster based routing algorithms. Simulation results are reported. Simulation results about the relationship between switch buffer size, injected traffic load, packet delay, packet drop probability and energy dissipation are analyzed. On comparing CBT with GBT, a significant performance improvement is demonstrated. © 2011 IEEE.


cited By (since 1996)3; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@64d97a2e ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@1e495bc Through org.apache.xalan.xsltc.dom.DOMAdapter@46226a9c; Conference Code:87395

Cite this Research Publication

Na Viswanathan, Paramasivam, Kb, and Dr. Somasundaram K., “Performance analysis of cluster based 3D routing algorithms for NoC”, in 2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, Trivandrum, Kerala, 2011, pp. 157-162.