Publication Type:

Journal Article


Applied Mathematical Sciences, Hikari Ltd., Volume 7, Number 81-84, p.4173-4184 (2013)



The packet switching based Network-on-Chip (NoC) is an obvious interconnect design alternative to the shared bus, crossbar or ring based on-chip communication architecture used in System-on-Chips (SoCs). The advent of the three dimensional NoC (3D NoC) architecture attracts added interest as it offers improved performance and shorter global interconnect. In the 3D NoC architecture, topology plays a vital role in determining the performance of the interconnect architecture. The performance and cost metrics of the 3D NoC topology are evaluated by using simulation in general. However, analytical models provide more insights on how the traffic related parameters influence the performance of the topology. In this paper, the traffic related parameters of a 3D NoC topology, namely 3D Recursive Network Topology (3D RNT) are evaluated by using network calculus based methodology and the results of the evaluation are compared against the results produced using simulation. © 2013 N. Viswanathan et al.


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Cite this Research Publication

N. Viswanathan, Paramasivam, K., and K. Somasundaram, “Performance and cost metrics analysis of a 3D NoC topology using network calculus”, Applied Mathematical Sciences, vol. 7, pp. 4173-4184, 2013.