Nowadays, System-on-Chips (SoCs) designers are forced to integrate tens to hundreds of functional and storage blocks in a single die to implement emerging complex computation, multimedia and network services. The integration of huge degree of the blocks in a single die poses new challenge in designing the interconnect architecture of the blocks in SoCs. The traditional bus based interconnect infrastructure is ineffective as the number of the blocks increases more than ten. The packet based Network- on- Chip (NoC) is an obvious interconnect design alternative to the bus based on-chip communication architecture in SoCs. The advent of 3D NoC architecture attracts added interest as it offers improved performance and shorter global interconnect. Evolving an efficient 3D network topology and developing 3D routing scheme play a crucial role in determining the performance of 3D NoC interconnect architecture. In this paper, two 3D NoC topologies, namely 3D Recursive Network Topology (3D RNT) and 3D Modified Mesh Topology (3D MMT) are presented. End-to-end delay, switch buffer size and the influence of the buffer size in determining area overhead requirement of the two topologies are evaluated using an analytical model of network calculus and the evaluation results of the two topologies are compared. It is shown that the 3D RNT outperforms the 3D MMT even though 50% of the vertical links are trimmed down in the former topology. Further, 20 % reduction in average switch buffer size and 16% reduction in area overhead requirement are achieved in the 3D RNT. The results of the analysis are of use to evaluate and optimize 3D NoC interconnect architecture as far as the design space is concerned.
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Na Viswanathan, Paramasivam, Kb, and Dr. Somasundaram K., “Performance comparison of 3D NoC topologies using network calculus”, Life Science Journal, vol. 10, pp. 4379-4385, 2013.