This paper analyzes possible performance improvement of streaming applications by the parallel computation platform of FPGAs. Software developers still are not familiar with the hardware implementation details of applications and will benefit from this analysis. First the available logic and memory resources of modern FPGAs like Xilinx's Virtex-5 and Virtex-6 devices are explored to determine how many parallel processors can be configured with the available logic resources and how many parallel processors' speed can be sustained by simultaneous data access from the on-chip memory. A portion of the on-chip memory is first set aside for pre-fetching of reconfiguration bits for dynamic reconfiguration of FPGA. The rest of the on-chip memory is used for data memory requirements of the concurrent processors. Based on input data rate and required output throughput of data, a number of on-chip cache memory locations and their sizes are determined. Finally a quantitative analysis of possible performance gain of streaming applications by FPGA implementation is compared to that of sequential implementations by a 2.5 GHz dual-core Intel microprocessor. © 2010 IEEE.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@762b5c77 ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@18c3c53d Through org.apache.xalan.xsltc.dom.DOMAdapter@5cca347e; Conference Code:80938
Ra Guha and Al-Dabass, Db, “Performance prediction of parallel computation of streaming applications on FPGA platform”, in UKSim2010 - UKSim 12th International Conference on Computer Modelling and Simulation, Cambridge, 2010, pp. 579-585.