Publication Type:

Conference Paper

Source:

International Conference on Advancements in Power and Energy (TAP Energy), 2015 , IEEE, Kollam (2015)

URL:

Kollam

Keywords:

antiphase disposition PWM method, Bridge circuits, carrier overlap PWM method, cascaded multilevel inverter topology, Drives, gate drive circuitry, Harmonic analysis, harmonic distortion, heat losses, in-phase disposition PWM method, Inverters, LC filter, minimum THD, Multilevel inverter, power conversion harmonics, Power harmonic filters, Power switches, Pulse width modulation, pulse width modulation technique, PWM invertors, PWM technique, Silicon, Switches, switching convertors, Switching stress, three phase 11-level inverter performance, total harmonic distortion, variable frequency PWM method

Abstract:

As compared to conventional inverter topologies like diode clamped and capacitor clamped inverters, the cascaded multilevel inverter has lesser harmonics as well as lower switching stress. The cascaded topology has more number of power switches leading to greater heat losses, larger size, higher cost and more gate drive circuitry. The proposed configuration contains less number of switches and produces lesser harmonics in the output voltage than the cascaded topology. A comparison between four different types of pulse width modulation (PWM) techniques, namely, In-phase disposition (IPD), Anti-phase disposition (APD), Carrier Overlap (CO) and Variable Frequency (VF) PWM methods, has been done. The results have been verified through simulation study in MATLAB/Simulink in order to select the best PWM method that provides minimum THD in the output voltage. An LC filter has been designed to improve the harmonic profile.

Cite this Research Publication

R. Nair, Mahalakshmi, R., and Thampatty, K. C. S., “Performance of three phase 11-level inverter with reduced number of switches using different PWM techniques”, in International Conference on Advancements in Power and Energy (TAP Energy), 2015 , Kollam, 2015.