Pipelined ADC based design of bandpass ΔΣ-ADC

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Abstract:

A high-speed, large dynamic range fS/4 bandpass ΔΣ-modulator using a first-order error-feedback loop is proposed. The internal quantiser is realised using a high-speed pipelined ADC. Error feedback is achieved by exploiting the implicit latency in a pipelined ADC. The proposed architecture achieves an SNR of 94 dB with an OSR of 32. © The Institution of Engineering and Technology 2013.

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