In this paper, a comparison-free sorting algorithm is proposed for negative and positive elements which satisfies the conditions such as hardware complexity. The basic idea is to sort the array of input integer elements without performing any comparison related operations between the data. Sorting technique for negative and positive numbers are executed involving similar hardware. Therefore, it doesn't require any complex hardware design. This avoids any usage of memory such as SRAM or any circuitry involving complex design as compared to that of the ones used in other conventional sorting practices. Instead the proposed work utilizes basic registers to store the binary elements. FSM module is proposed with a comparison-free sorting algorithm in order to reduce hardware complexity. All the designs are coded in VHDL and verified using ModelSim SE10.4d simulator. The conventional and the proposed design are synthesized using Vivado and Synopsys DC Design Compiler (90 nm CMOS technology). From the synthesis report, it is observed that proposed FSM with comparison-free sorting algorithm has reduction in power and area compared to the conventional design.
cited By 0; Conference of 4th International Symposium on Signal Processing and Intelligent Recognition Systems, SIRS 2018 ; Conference Date: 19 September 2018 Through 22 September 2018; Conference Code:222839
T. A. S. Bhargav and Prabhu E., “Power and Area Efficient FSM with Comparison-Free Sorting Algorithm for Write-Evaluate Phase and Read-Sort Phase”, in Advances in Signal Processing and Intelligent Recognition Systems, Singapore, 2019, vol. 968, pp. 433-442.