Publication Type:

Conference Paper

Source:

2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI) (2018)

Keywords:

Adders, approximate multiplier, Delay effects, delay efficient exact adder, Delays, Digital signal processing, DSP, embedded data processors, Energy efficiency, error tolerance, error tolerance adder, ETA designs, Logic design, Microprocessor chips, multiplying circuits, Power demand, Power dissipation, power efficient exact adder, power utilization, time delay, Very large scale integration, VLSI, word length 16 bit, word length 32.0 bit, word length 4 bit, word length 8 bit

Abstract:

Approximate results are required in many embedded data processors as they reduce time delay and power. As error tolerance adder (ETA) has decreased power drastically trading with accuracy. This work focuses on reducing delay on existing adders when replaced with a fast adder. When compared to the past works on ETA, the proposed work has high power utilization and more accuracy of speed. The proposed design is compared and synthesized for the power and delay. When observed the existing ETA designs, the proposed work achieves significant improvement in power dissipation about 17.13%, 4.6%, 15.4%, 5.35% decrement for 4, 8, 16, 32 bits respectively, and significant improvement in delay about 28.90%, 23.59%, 20.08%, 24.44% decrement for 4, 8, 16, 32 bits respectively.

Cite this Research Publication

V. V. Kavipranesh, Janarthanan, J., Amruth, T. N., Harisuriya, T. M., and Prabhu E., “Power And Delay Efficient Exact Adder For Approximate Multiplier”, in 2018 International Conference on Advances in Computing, Communications and Informatics (ICACCI), 2018.