Publication Type:

Conference Paper

Source:

Information Processing and Management, Springer Berlin Heidelberg, Berlin, Heidelberg (2010)

ISBN:

9783642122149

URL:

https://link.springer.com/chapter/10.1007/978-3-642-12214-9_20

Abstract:

The power consumption of the integrated circuits have become increasingly a central topic of today's research. The need for low power has caused a major paradigm shift where power dissipation has become as important as performance and area. In this paper the original direct mapped cache of Alpha AXP 21064 processor is modified into set associative and phased set associative caches. The experimental results show that phased set associative cache is more power efficient than set associative cache. These three designs namely direct mapped, set associative and phased set associative caches are modeled using Verilog HDL, simulated in Modelsim and synthesized in Xilinx ISE 10.1. The power estimation and analysis is done using Xilinx XPower Analyser.

Cite this Research Publication

Rajesh Kannan Megalingam, Deepu, K. B., Iype, J. P., Parthasarathy, R., and Gautham, P., “Power Consumption Analysis of Direct, Set Associative and Phased Set Associative Cache Organizations in Alpha AXP 21064 Processor”, in Information Processing and Management, Berlin, Heidelberg, 2010.