Publication Type:

Conference Paper

Source:

Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, p.529-533 (2009)

ISBN:

9781424445196

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-70449094916&partnerID=40&md5=10ea6418a33ae367a5aff7dbe51f8a90

Keywords:

BHT, BTB, Clocks, Computer science, Dual edge triggered clock, Electric power utilization, ILP, Information technology, LDPR, Pipelines, power, RISC pipeline datapath

Abstract:

Power consumption and performance are the crucial factors that determine the reliability of a CPU. In this paper, we discuss about some techniques that can be used for Instruction Level Parallelism which enhances the performance of the CPU by reducing the CPI there by reducing power consumption. We have also discussed about the power saving scheme using proper clocking strategies. We have mainly focused on implementing the simplified RISC pipeline datapath in HDL using two different clocking schemes to reduce the power consumption. We have adopted a new method which uses dual edge triggered clock that can decrease the power consumption of a pipelined datapath considerably, without sacrificing the throughput of the CPU. Finally, we have given the experimental result for our implementation of simplified RISC datapath. © 2009 IEEE.

Notes:

cited By 1; Conference of 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009 ; Conference Date: 8 August 2009 Through 11 August 2009; Conference Code:78148

Cite this Research Publication

Rajesh Kannan Megalingam, T. Hassan, S., Vivek, P., Mohan, A., and M. Rao, T., “Power consumption reduction in CPU datapath using a novel clocking scheme”, in Proceedings - 2009 2nd IEEE International Conference on Computer Science and Information Technology, ICCSIT 2009, Beijing, 2009, pp. 529-533.

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