Publication Type:

Conference Paper


Information Processing and Management, Springer Berlin Heidelberg, Berlin, Heidelberg (2010)





Power efficiency in VLSI design is in prime focus in today's state of the art. A simple method of reducing power consumption in cache memories and other logic is presented here. We make use of both edges of clock signals to perform cache accesses in order to enable the reduction of operating frequency - and thus, dynamic power - without affecting performance to a large extent. Experimental results are presented, making use of the OpenSPARC T1 and Alpha AXP 21064 processor caches.

Cite this Research Publication

Rajesh Kannan Megalingam, Arunkumar, M., V. Ashok, A., Nived, K., and Daniel, C. J., “Power-Efficient Cache Design Using Dual-Edge Clocking Scheme in Sun OpenSPARC T1 and Alpha AXP Processors”, in Information Processing and Management, Berlin, Heidelberg, 2010.