Publication Type:

Journal Article

Source:

Communications in Computer and Information Science, Volume 70, p.108-113 (2010)

ISBN:

9783642122132

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-77950552020&partnerID=40&md5=68d60c4f40cc00743351c96c51a30eb2

Keywords:

Cache access, Cache memory, Clock signal, Clocking schemes, CMOS integrated circuits, Data processing, Dynamic Power, Dynamic power dissipation, Operating frequency, Power efficiency, Power efficient, Prime-focus, Processor cache, Reducing power, SIMPLE method, State of the art, VLSI design

Abstract:

Power efficiency in VLSI design is in prime focus in today's state of the art. A simple method of reducing power consumption in cache memories and other logic is presented here. We make use of both edges of clock signals to perform cache accesses in order to enable the reduction of operating frequency - and thus, dynamic power - without affecting performance to a large extent. Experimental results are presented, making use of the OpenSPARC T1 and Alpha AXP 21064 processor caches. © 2010 Springer-Verlag Berlin Heidelberg.

Notes:

cited By (since 1996)0

Cite this Research Publication

R. K. Megalingam, Arunkumar, M., Ashok, V. A., Nived, K., Daniel, C. J., V.V., D., R., V., N.C., D., S., J., N., M., S., S., P.M., T., and F.L., G., “Power-efficient cache design using dual-edge clocking scheme in sun openSPARC T1 and alpha AXP processors”, Communications in Computer and Information Science, vol. 70, pp. 108-113, 2010.