Low power VLSI has received tremendous attention due to power constraints in designs. This paper details a survey on switching activity estimation techniques. It also presents a computationally efficient activity estimator which is probabilistic in nature. This estimator is faster and accurate. Simulation based approach is practically impossible for large circuits. More statistical parameters related to activity estimation are incorporated to improve the accuracy. This methodology is implemented on MCNC benchmarks. LUT mapping is done using the logic synthesis tool ABC. Spatial correlation is considered by computing the activities at each LUT. Power estimation using Synopsys Design Compiler tool gave 18% reduction in dynamic power for optimized circuits. Timing analysis plays an important role in circuit design. Statistical Timing Analysis (STA) is performed and the delay analysis is obtained. An effective tradeoff between timing and power were reported. © Research India Publications.
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Ramesh S. R. and Jayaparvathy, R., “Probabilistic activity estimator and timing analysis for LUT based circuits”, International Journal of Applied Engineering Research, vol. 10, pp. 33238-33242, 2015.