Publication Type:

Conference Paper

Source:

Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, Lake Como, Italy (2008)

URL:

http://www.hni.uni-paderborn.de/publikationen/publikationen/?tx_hnippview_pi1%5Bpublikation%5D=4630&tx_hnippview_pi1%5Bfelder%5D%5Blade%5D=1416

Abstract:

High performance requirements often necessitate redesigns for every new application, resulting in long time-tomarket. Every architectural change involves costs in terms of hardware design, verification and fabrication. As an alternative, architectural flexibility provides easy adaptability to different application domains in order to avoid the high cost of redesigns. Hence, a method of reusing the basic building blocks within processors to enable co-operative multiprocessing is proposed. Runtime reconfiguration is used as a method for application-specific customisation. Here, a method of application description in conjunction with a flexible multiprocessor template is proposed. Finally, the costs and benefits of this approach are analysed for a computationally intensive algorithm in terms of execution time and power consumption. The impact of variations in applicationspecific characteristics on the proposed architecture, are also analysed.

Body: 

High performance requirements often necessitate redesigns for every new application, resulting in long time-tomarket. Every architectural change involves costs in terms of hardware design, verification and fabrication. As an alternative, architectural flexibility provides easy adaptability to different application domains in order to avoid the high cost of redesigns. Hence, a method of reusing the basic building blocks within processors to enable co-operative multiprocessing is proposed. Runtime reconfiguration is used as a method for application-specific customisation. Here, a method of application description in conjunction with a flexible multiprocessor template is proposed. Finally, the costs and benefits of this approach are analysed for a computationally intensive algorithm in terms of execution time and power consumption. The impact of variations in applicationspecific characteristics on the proposed architecture, are also analysed.

Cite this Research Publication

Dr. Madhura Purnaprajna and Porrmann, M., “Run-time Reconfigurable Cluster of Processors”, in Proceedings of 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), Workshop on Design, Architecture and Simulation of Chip Multi-Processors, IEEE Computer Society, Lake Como, Italy, 2008.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
9th
RANK(INDIA):
NIRF 2017
150+
INTERNATIONAL
PARTNERS