Publication Type:

Conference Paper

Source:

NASA/ESA Conference on Adaptive Hardware and Systems, 2009. AHS 2009. , IEEE, San Francisco, CA (2009)

ISBN:

9780769537146

Accession Number:

10966769

URL:

http://www.scopus.com/record/display.url?eid=2-s2.0-72849113628&origin=resultslist&sort=plf-f&src=s&st1=Run-time+reconfigurability+in+embedded+multiprocessors&nlo=&nlr=&nls=&sid=9F816727778C5E0467E6037EBF626F71.N5T5nM1aaTEF8rE6yKCR3A%3a1530&sot=b&sdt=cl&c

Abstract:

A dynamically reconfigurable on-chip multiprocessor architecture is presented, which can be adapted to changing application demands and to faults detected at run-time. The scalable architecture comprises lightweight embedded RISC processors that are interconnected by a hierarchical network-on-chip (NoC). Reconfigurability is integrated into the processors as well as into the NoC with minimal area and performance overhead. Adaptability of the architecture relies on a self-optimizing reconfiguration of the MPSoC at run-time. The resource-efficiency of the proposed architecture is analyzed based on FPGA and ASIC prototypes.

Cite this Research Publication

M. Porrmann, Dr. Madhura Purnaprajna, and Puttmann, C., “Self-optimization of mpsocs targeting resource efficiency and fault tolerance”, in NASA/ESA Conference on Adaptive Hardware and Systems, 2009. AHS 2009. , San Francisco, CA, 2009.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
9th
RANK(INDIA):
NIRF 2017
150+
INTERNATIONAL
PARTNERS