At speed digital gain error calibration of pipelined ADCs
Publication Type:Conference Paper
Source:Conference Proceedings - 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015, Institute of Electrical and Electronics Engineers Inc. (2015)
This paper proposes a full speed digital gain error calibration technique for pipelined ADCs. The calibration takes care of both finite op-amp gain and capacitor mismatch. Unlike previous calibration techniques that use resistor ladder to generate the calibration signal, the proposed technique uses capacitors switching to reference voltages to eliminate the large RC time constants associated with resistor ladder. The proposed technique also facilitates the calibration to happen at full speed overcoming the drawbacks of existing foreground calibration techniques. 12-bit ADCs with first stage resolution of 1.5-bit, 2.5-bit, 3.5-bit, and 2-bit, followed by an ideal back-end ADC were simulated in system level using MATLAB and then at circuit level in Cadence. The circuit simulations incorporate various non-idealities like finite op-amp gain, op amp settling, and capacitor mismatch. Circuit level simulations in Global Foundry's (GF) 55-nm process with an an open loop op amp gain of 50 dB and capacitor mismatch of ±3% show that the calibration method improves the SFDR by more than 30 dB and SNDR by more than 25 dB. © 2015 IEEE.
cited By 0; Conference of 13th IEEE International NEW Circuits and Systems Conference, NEWCAS 2015 ; Conference Date: 7 June 2015 Through 10 June 2015; Conference Code:115654