Publication Type:

Conference Paper

Source:

2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, Institute of Electrical and Electronics Engineers Inc. (2015)

ISBN:

9781479978489

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84965082017&partnerID=40&md5=2698dac4185dbbf6a51966d1ebaabcda

Keywords:

Artificial intelligence, Body biasing, CMOS integrated circuits, Computation theory, Leakage currents, Leakage power, Read stability, Sleep transistors, Subthreshold, Transistors

Abstract:

<p>In this paper, a Modified Differential 8T SRAM cell is proposed for subthreshold region of operation. Forward Body biasing technique is used to improve the drivability of transistors and sleep transistor logic is used to reduce the leakage current in standby mode. The proposed design is implemented with 45 nm CMOS technology and is simulated using Cadence Virtuoso Simulator. At 0.5 V supply voltage, the read SNM and write SNM are 98 mV and 112 mV respectively and these are 32% and 21% higher than there reported in literature. The leakage current and power consumption of the cell are 3.26 fA and 1.63 fW respectively. © 2015 IEEE.</p>

Notes:

cited By 0; Conference of 6th IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015 ; Conference Date: 10 December 2015 Through 12 December 2015; Conference Code:120030

Cite this Research Publication

P. Sreelakshmi, Pande, K. S., and Dr. N.S. Murty, “SRAM cell with improved stability and reduced leakage current for subthreshold region of operation”, in 2015 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2015, 2015.

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