A new flexible logic Built in Self-Test (BIST) scheme that has complete reconfigurability is presented. This technique uses a Linear Feedback Shift Register (LFSR), Multiple Input Signature Register (MISR) and a Bist controller; all of them programmable to work with any scan based design and targeted to detect all possible single stuck at faults. The seed activated LFSR generates exhaustive test patterns which are applied on any Design Under Test (DUT) and responses are received at the output of the scan chains in the DUT and the responses are compressed to produce a signature. It is shown that this scheme works with multiple designs without any structural modification in the BIST blocks. This technique is well suited to work with any scan based sequential design. A maximum number of 100 scan chains supported which can be increased. It eliminates the drawback of creating new bist logic for different blocks of a single System on Chip (SoC). Parallel testing of different blocks within a SoC is also possible within the power limits. The Reconfigurable Logic BIST (RLBIST) is checked in six designs and techniques are adopted to optimize the testpatterns with the help of cadence Encounter true time 13.1 ATPG. It is shown that the speed, power and area of the DUT are not affected by the reconfigurable BIST structures.
J. Sirisha, C., N. Vaishnavi, P., N. K., S., S. Vidhya, G., Y., Balamurugan, K., Dr. Nirmala Devi M., and M., J., “Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models”, International Conference on Communication and Computing, ICC 2014. Elsevier, Bangalore, India, pp. 1-8, 2014.