Publication Type:

Journal Article


Smart Innovation, Systems and Technologies, Springer Science and Business Media Deutschland GmbH, Volume 79, p.637-650 (2018)





Array references, C (programming language), Codes (symbols), Embedded application, Embedded systems, Hardware, High Level Synthesis, Hybrid systems, Input size, Loop unrolling, Memory access patterns, Memory architecture, Sequential ordering, Software designers, Timing requirements


<p>CPU/FPGA hybrid systems have emerged as a viable means to achieve high performance in the field of embedded applications and computing. High-Level Synthesis (HLS) tools facilitate software designers and programmers to utilize the underlying hardware in a hybrid system without requiring deep insights into hardware. HLS tools execute the program in sequential order by default. However, these tools provide mechanisms to parallelize the code wherein the user/programmer can apply constructs such as loop-unrolling, loop-flattening, and pipelining in the form of pragmas. Along with all these constructs in place, it is also important for programmers to understand the memory access pattern used in the program for efficiently utilizing the underlying capabilities of CPU/FPGA hybrid system. Memory access patterns in array references play a major role in deciding the latency and area required for a specific computation. Four typical memory access patterns with growing input sizes in array context were exercised in Vivado HLS with C code as an input and it was observed that change in the memory access pattern leads to a different area and timing requirements and change in the coding style may improve the performance of HLS tools. © 2018, Springer Nature Singapore Pte Ltd.</p>


cited By 0; Conference of 1st International Conference on Smart System, Innovations and Computing, SSIC 2017 ; Conference Date: 15 April 2017 Through 16 April 2017; Conference Code:209779

Cite this Research Publication

M. Belwal and Sudarshan, T. S. B., “A study of memory access patterns as an indicator of performance in high-level synthesis”, Smart Innovation, Systems and Technologies, vol. 79, pp. 637-650, 2018.