The equivalent oxide thickness (EOT) of high-k n-channel metal oxide semiconductor (NMOS) transistors was scaled using 3 methods, Formula reduction of the bottom interfacial layer (BIL) using Formula interface engineering, Formula thickness reduction of the Formula dielectric, and Formula use of metal gate electrodes to minimize top interfacial growth formation and polysilicon depletion. NMOS transistors fabricated using these methods demonstrate 0.72 nm EOT using the Formula BIL with scaled Formula /metal gates and 0.81 nm EOT using the Formula BIL with scaled Formula /metal gates. Charge pumping, mobility, and device performance results of these high-k NMOS transistors is discussed. © 2004 The Electrochemical Society. All rights reserved.
J. J. Peterson, Young, C. D., Barnett, J., Dr. Sundararaman Gopalan, Gutt, J., Lee, C. - H., Li, H. - J., Hou, T. - H., Kim, Y., Lim, C., and , “Subnanometer scaling of HfO2/metal electrode gate stacks”, Electrochemical and solid-state letters, vol. 7, pp. G164–G167, 2004.