Publication Type:

Patent

Source:

Number PCT/IB2012/057462 (2014)

URL:

https://www.google.com/patents/WO2014049402A1?cl=en

Abstract:

Embodiments of the disclosure relate to a method and system for Built-in-Self- Test of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of sub-sampled signals, thus giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair.

Cite this Research Publication

Dr. Rajath Vasudevamurthy and Amrutur, B., “System and method for Built-In Self Test (BIST) in an integrated circuit”, U.S. Patent PCT/IB2012/0574622014.

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