Publication Type:

Journal Article

Source:

International Journal of Signal and Imaging Systems Engineering, Volume 5, Number 3, p.158-166 (2012)

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-84867863475&partnerID=40&md5=c86ac409a8e8c9410e8f1b3b7256cb6a

Abstract:

This paper describes Full Search Block Matching Algorithm (FSBMA) performed on 3D image in the transformed domain. An image of size N×N×8 is first transformed in to eight sub bands each of size N/2 × N/2 × 4 employing 3D Discrete Wavelet Transform (3D DWT). FSBMA performed on LLL sub band component which achieves good Peak Signal to Noise Ratio (PSNR), Compression Ratio (CR) and reduces computation complexity when compared with the original image. Modified lifting scheme based DWT and Systolic Array Architecture (SAA) based FSBMA are implemented on Field Programmable Gate Array (FPGA). 3D DWT implemented on FPGA operates at 230 MHz and consumes a power of 0.29 W, while FSBMA implemented on FPGA to reduce the computational time for motion estimation, operates at 120 MHz and consumes a power less than 0.34 W. Copyright © 2012 Inderscience Enterprises Ltd.

Notes:

cited By (since 1996)0

Cite this Research Publication

G. Hegde and Vaya, P., “Systolic array based motion estimation architecture of 3D DWT sub band component for video processing”, International Journal of Signal and Imaging Systems Engineering, vol. 5, pp. 158-166, 2012.

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