Energy reduction is an important factor and a challenge in the design of the embedded system. In this work, we propose TEST, a process-aware partitioning scheme to study the impact of partitioning scheme based on process aware in instruction cache for multitasking embedded system. Process-aware partitioning will partition instruction cache which is based on the mapping between process and cache memory. This technique results in 70–80% reduction in dynamic energy and 50–70% in static leakage energy as compared to the base set-associative cache architecture. Results of the TEST are evaluated using the simple scalar 3.0 simulator using the Mi-bench-embedded benchmarks. © 2018, Springer Nature Singapore Pte Ltd.
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B. R. Upadhyay and Sudarshan, T. S. B., “Task-enabled instruction cache partitioning scheme for embedded system”, Smart Innovation, Systems and Technologies, vol. 79, pp. 603-612, 2018.