Publication Type:

Journal Article

Source:

Smart Innovation, Systems and Technologies, Springer Science and Business Media Deutschland GmbH, Volume 79, p.603-612 (2018)

ISBN:

9789811058271

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-85041513503&doi=10.1007%2f978-981-10-5828-8_58&partnerID=40&md5=87f8c94a5910667a4ea5a7111f3df612

Keywords:

Base set, Buffer storage, Cache memory, Cache partitioning, Dynamic energy, Embedded benchmarks, Embedded systems, Energy reduction, Instruction caches, Process aware cache, Static leakage

Abstract:

<p>Energy reduction is an important factor and a challenge in the design of the embedded system. In this work, we propose TEST, a process-aware partitioning scheme to study the impact of partitioning scheme based on process aware in instruction cache for multitasking embedded system. Process-aware partitioning will partition instruction cache which is based on the mapping between process and cache memory. This technique results in 70–80% reduction in dynamic energy and 50–70% in static leakage energy as compared to the base set-associative cache architecture. Results of the TEST are evaluated using the simple scalar 3.0 simulator using the Mi-bench-embedded benchmarks. © 2018, Springer Nature Singapore Pte Ltd.</p>

Notes:

cited By 0; Conference of 1st International Conference on Smart System, Innovations and Computing, SSIC 2017 ; Conference Date: 15 April 2017 Through 16 April 2017; Conference Code:209779

Cite this Research Publication

B. R. Upadhyay and Sudarshan, T. S. B., “Task-enabled instruction cache partitioning scheme for embedded system”, Smart Innovation, Systems and Technologies, vol. 79, pp. 603-612, 2018.

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