Publication Type:

Journal Article

Source:

Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, Number 119-125, Las Vegas, Nevada, USA (2009)

Abstract:

Parallelism and adaptability are two distinct architectural design considerations in embedded processors. Multicore processors accelerate application execution on account of their inherent parallelism and run-time reconfiguration capabilities add adaptability during infield deployment. To benefit from both these features, a reconfigurable multiprocessor architecture − QuadroCore has been developed. A novel reconfiguration
mechanism has been incorporated that provides fast run-time adaptability in a 4-processor cluster. In this paper, this scheme of reconfiguration has been used to save energy when using QuadroCore for data-parallel applications. As a proof of concept, a data-intensive neural network application called Self-organising Maps has been implemented on QuadroCore. Via reconfiguration, energy reduction of up to 30% has been observed for an
implementation in UMC’s 90nm standard cell technology.

Cite this Research Publication

Dr. Madhura Purnaprajna, Pohl, C., Porrmann, M., and Rueckert, U., “Using Run-time Reconfiguration for Energy Savings in Parallel Data Processing”, Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, ERSA'09, 2009.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS