Publication Type:

Journal Article

Source:

(0)

Abstract:

Caches in Chip Multiprocessors (CMPs) are organized as private L1 caches or large shared L2 cache or both. Most of the recent researchers have focused on architectural and circuit techniques to increase performance. Variable Forwarding Cache Coherency combines the advantages of private caches and shared caches, i.e., low latency of L1 and miss rate of shared L2. This paper proposes a methodology to improve performance of the system by using variable forwarding cache coherence technique in CMPs.

Cite this Research Publication

A. Roy, Vadlamani, S., and Sudarshan, T. S. B., “Variable Forwarding Cache Coherence for Chip Multiprocessors”.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
8th
RANK(INDIA):
NIRF 2018
150+
INTERNATIONAL
PARTNERS