Publication Type:

Conference Proceedings


Communications and Signal Processing (ICCSP), 2014 International Conference on, p.748-752 (2014)

Accession Number:



Bit Serial, bit serial multiplication, bit-serial multiplier, Clocks, CMOS integrated circuits, CMOS technology, critical path delay, Cryptography, finite field GF (2m), Galois field, Galois fields, gated clock technique, irreducible polynomial degree, Logic gates, low-power electronics, LSB-First multiplier, maximum clock frequency, most significant bit, MSB, multiplying circuits, multiVth optimization techniques, optimisation, Polynomial Basis, Polynomials, power aware computing, Power Consumption, power gating, Reconfigurable architecture, Reconfigurable architectures, registers, Table lookup, versatile polynomial basis multiplier, Versatility


A novel and efficient architecture for a versatile polynomial basis multiplier over GF(2m) is dealt with. The value m; of the irreducible polynomial degree, can be changed and so the multiplier can be configured and programmed. Thus versatility of the multiplier refers to its reconfigurable property. The architecture deals with an efficient execution of the Most Significant Bit (MSB)-First, bit serial multiplication for different operand lengths. The attractive features of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) Low power consumption by employing the gated clock technique, power gating and Multi Vth optimization techniques (d) improvement of maximum clock frequency due to the lessening of critical path delay.

Cite this Research Publication

R. M, E. Prabhu, and H, M., “A versatile low power design of bit-serial multiplier in finite fields GF (2m)”, Communications and Signal Processing (ICCSP), 2014 International Conference on. pp. 748-752, 2014.