A versatile low power design of bit-serial multiplier in finite fields GF (2m)

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Abstract:

A novel and efficient architecture for a versatile polynomial basis multiplier over GF(2m) is dealt with. The value m; of the irreducible polynomial degree, can be changed and so the multiplier can be configured and programmed. Thus versatility of the multiplier refers to its reconfigurable property. The architecture deals with an efficient execution of the Most Significant Bit (MSB)-First, bit serial multiplication for different operand lengths. The attractive features of the proposed architecture are (a) its flexibility on arbitrary Galois field sizes, (b) its hardware simplicity which results in small area implementation, (c) Low power consumption by employing the gated clock technique, power gating and Multi Vth optimization techniques (d) improvement of maximum clock frequency due to the lessening of critical path delay.