Multiply and accumulate function is the important part of digital signal processing algorithms. This can be implemented more effectively with distributed arithmetic (DA) architecture . These architectures make extensive use of look-up tables, which make them ideal for implementing digital signal processing functions on Xilinx FPGAs. An emerging arithmetic-intensive digital signal processing algorithm is the discrete wavelet transform (DWT) which have proven to be extremely useful for image and video coding applications like MPEG-4 and JPEG 2000. But the limitation of this architecture is that the size of look-up tables get increased exponentially as the constant coefficients of wavelet used for these applications increases. In this paper, we proposed a novel methodology to implement the Burrows wheeler transform (BWT)  block in FPGA for achieving memory reduced DA. © 2012 ICST Institute for Computer Science, Social Informatics and Telecommunications Engineering.
cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@75260146 ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@121dd6c0 Through org.apache.xalan.xsltc.dom.DOMAdapter@64fde08a; Conference Code:95506
A. S. Remya Ajai, Rajan, L., and Shiny, C., “VLSI implementation of Burrows wheeler transform for memory reduced distributed arithmetic architectures”, Lecture Notes of the Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, vol. 108 LNICST, pp. 242-245, 2012.