Publication Type:

Conference Proceedings

Source:

2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), p.280-284 (2020)

URL:

https://ieeexplore.ieee.org/document/9076498

Keywords:

application specific integrated circuit, Application specific integrated circuits, ASIC, Cadence NCLaunch, Cadence tools, codeword, Decoder, Decoding, Error correction capability, Error correction codes, field programmable gate array, Field programmable gate arrays, FPGA, GDSII file, LFSR, Octave tools, parity bits, Peterson Gorenstein Zierler algorithm, PetersonGorenstein-Zierler (PGZ), QuestaSim, Reed Solomon, Reed Solomon codes, Reed Solomon encoding, Reed-Solomon codes, RS codes, Very Large Scale Integration(VLSI), Vivado, Vivado tools, VLSI, VLSI implementation

Abstract:

Reed Solomon(RS) codes are error correction codes that are widely used in communication systems. RS codes exhibits high error correction capability as compared with other error correction codes. Encoding is the process of adding parity bits to the input messages. The input message and parity bit together form the codeword. The input of the decoder can contain errors. In decoding, the original message is retrieved by applying different algorithms to the codeword. This paper uses LFSR for encoding and the Peterson Gorenstein Zierler algorithm for decoding. This work is aimed at execution of RS codes using different technologies. The Reed Solomon encoding and decoding is done using Octave, Vivado, Cadence tools. The data is tested for a single error and two errors. The system is implemented and synthesized in Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). Timing analysis has been done and GDSII file has been generated.

Cite this Research Publication

Syam Krishnan T., Anu Chalil, and K. N. Sreehari, “VLSI Implementation of Reed Solomon Codes”, 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC). pp. 280-284, 2020.