Publication Type:

Journal Article

Source:

International Journal of Mathematical Modelling and Numerical Optimisation, Inderscience Enterprises Ltd., Volume 7, Number 1, p.83-96 (2016)

URL:

https://www.scopus.com/inward/record.uri?eid=2-s2.0-84970038657&partnerID=40&md5=fb8550155b8d02e75c914d41b6cb2315

Abstract:

<p>This paper presents a new zero suppressed binary decision diagram (ZBDD)-based approach for obtaining larger number of relaxed bits. These test sets find major application in reducing the power consumed during testing. Experiments performed on single and multiple stuck-at faults using ZBDDs show better results in terms of percentage of relaxation over the existing comparable BDD-based approaches. Moreover using these relaxed test vectors and by suitable X-filling methods average switching activity (ASA) of the circuit can be reduced, which will reduce the power dissipation during testing. © Copyright 2016 Inderscience Enterprises Ltd.</p>

Notes:

cited By 0

Cite this Research Publication

N. Mohan and Dr. Anita J. P., “A zero suppressed binary decision diagram-based test set relaxation for single and multiple stuck-at faults”, International Journal of Mathematical Modelling and Numerical Optimisation, vol. 7, pp. 83-96, 2016.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
9th
RANK(INDIA):
NIRF 2017
150+
INTERNATIONAL
PARTNERS
  • Amrita on Social Media

  • Contact us

    Amrita Vishwa Vidyapeetham
    Amritanagar, Coimbatore - 641 112
    Tamilnadu, India