Project Incharge: 
Prof. Prabakar Poornachandran
Dr. Krishnashree Achuthan
Date: 
Saturday, January 1, 2011
Funding Agency: 
Private Security Firm

The project 'Security Event Processing Acceleration Using GPGPU' proposes to provide a proof of concept for building a FPGA based NIDS for highspeed network environments. The proposed FPGA based NIDS would employ a lightweight snort detection engine to filter packets based on predefined rules over packet headers and payloads.

The prime objective of this project is to offload the high number of string or rule or pattern matching computation to GPGPU in any Inline Alerter system/Security Event Processing Acceleration system. The pattern matching over security event streams are done using new complex algorithms.

The work will be extended for anonimising the alerts in SIEM systems. This work also has extensive applications in utilising GPGPU for DLP and other intrusion prevention systems.

207
PROGRAMS
OFFERED
5
AMRITA
CAMPUSES
15
CONSTITUENT
SCHOOLS
A
GRADE BY
NAAC, MHRD
9th
RANK(INDIA):
NIRF 2017
150+
INTERNATIONAL
PARTNERS