Research objectives

Cyber Security of Networks and Smart Infrastructure – Exploration of efficient approaches for creating secure and reliable architectures for smart grid and cyber physical infrastructure. Develop scalable techniques for malware detection in high speed network backbones.

PhD Program and Focus

Architectures for secure and reliable neaworks, smart grid and cyber physical systems

Funded projects

Malware detection based on FPGA, Sandboxing and Machine Learning (jointly with Dr. T. Gireesh Kumar of Center for Cyber Security and Dr. T. Senthil Kumar of CSE)


  1. Dhanesh, P., Harish Ram, D.S, A fast and scalable pattern matching scheme for NIDS using Z algorithm, International Journal of Applied Engineering Research, 10 (16), pp. 37563-37568, 2015
  2. Bhuvaneswari, M. C., DS Harish Ram, and R. Neelaveni. "Design Space Exploration for Scheduling and Allocation in High Level Synthesis of Datapaths." Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems. Springer India, 2015. 69-92.
  3. Balaji, A. Jayanth, and D S Harish Ram, "FPGA Based System For Denial Of Service Detection In Smart Grid." (2015)
  4. Nikhil, N. A., and D. S. Harish Ram. "Hardware implementation of quasigroup based encryption." Embedded Systems (ICES), 2014 International Conference on”. IEEE, 2014. 
  5. Ram, Dasanpotty Sai Harish, Mugasimangalam Chinnadurai Bhuvaneswari, and Suresh Umadevi, "Improved Low Power FPGA Binding of Datapaths from Data Flow Graphs with NSGA II-based Schedule Selection," ADVANCES IN ELECTRICAL AND COMPUTER ENGINEERING 13.4 (2013): 85-92.
  6. Ram, D. S., M. C. Bhuvaneswari, and Shanthi S. Prabhu, "A novel framework for applying multiobjective GA and PSO based approaches for simultaneous area, delay, and power optimization in high level synthesis of datapaths," VLSI design 2012 (2012).
  7. Yazhini, S. Anbu, and D. S. HarishRam, "High level synthesis of data flow graphs using integer linear programming for switching power reduction" Signal Processing, Communication, Computing and Networking Technologies (ICSCCN), 2011 International Conference on. IEEE, 2011
  8. Ram, DS Harish, M. C. Bhuvaneswari, and S. M. Logesh, "A novel evolutionary technique for multi-objective power, area and delay optimization in high level synthesis of datapaths," VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on. IEEE, 2011
  9. Logesh, S. M., DS Harish Ram, and M. C. Bhuvaneswari, "Multi-objective optimization of power, area and delay during high-level synthesis of DFG's—A genetic algorithm approach," Electronics Computer Technology (ICECT), 2011 3rd International Conference on. Vol. 1. IEEE, 2011.