Members

Major research objectives

  • VLSI Design & Testing – Development of efficient algorithms for VLSI testing and extending it to focus on low power concept with compression schemes
  • RF CMOS System design – Application of CMOS or GaN technology in the design of RF transceiver systems at L, S, and C bands
  • Hardware Security & Trust - Enhancing the security of VLSI chips in safety critical applications like missiles & biomedical implants
  • Computational Intelligence - Application the high potential intelligence concepts like Neural networks, Particle Swarm Optimization, Genetic Algorithms etc., on social and health related problems like perception engineering & cancer Diagnosis for the improvement  
  • Evolvable Hardware – Emulation of efficient and optimized algorithms on FPGAs to develop proof-of-concept.
  • To design novel RF/Analog Integrated Circuits with MOSFETs of gate length 65nm and smaller.
  • To develop novel circuit designs for high speed, high frequency, low-power and chip area efficient applications.
  • To design novel high frequency (RF/Microwave/millimetre wave) and high power output circuits for RF communication.
  • Implementation of the above ICs with RF/Analog MOSFET models of International foundries and subsequent fabrication in International foundries abroad, characterisation at home for International publications.
  • VLSI Design, FPGA logic architectures and Timing Analysis.  Activity Estimation in  Field Programmable Gate Array is the main Goal. Static Timing Analysis (STA) and Statistical static Timing Analysis (SSTA) are  incorporated into the activity estimator to predict the runtime.  Approaches like parallel processing can be incorporated to improve the efficiency.
  • To develop new circuit designs for high speed, low-power and area efficient applications. Further to characterize new and existing circuit simulators and/or improve speed and reduce power for digital simulation. Digital circuit devices have important applications in many fields including Signal processing, communications, sensing, transportation, avionics and space technology, and medical technology.
  • Antenna simulation modeling at microwave and millimeter wave frequency region .
  • EMI shielding at different frequency bands  by Design and Optimization of microwave absorbers
     

Selected UG/PG Projects

  • FPGA Implementation of Genetically Evolved Artificial Neural Networks For Effective Resource Utilization
  • A Power Aware Reordering Based Compression Scheme for Test Volume Reduction
  • Power Reduction and Defect Coverage Improvement in At-Speed Testing
  • FPGA Implementation of Feedforward Neural Network with Layer Multiplexing
  • Security Enhanced Testing Using Scrambling and Test Compression
  • Test Compression for Low-power Testing
  • Small-signal Modelling of GaN HEMT based Transistor using PSO
  • An Efficient FIR Filter Design Using Common Sub Expression Elimination Method
  • VLSI Implementation of Multimode Floating Point Adder and Multiplier
  • Design of RF CMOS LNA for Millimeter wave Technology
  • Reversible Logic Synthesis of Fault Tolerant Combinational Logic Circuits
  • VLSI implementation of an enhanced text compression technique based on Lempel-Ziv Welch Compression,
  • Malicious struck-at and somersault combinational Trojan design and detection.
  • Preventing Hardware Design Obfuscation by detecting hardware Trojan,
  • Compressive sensing for PPM Modulation
  • Design of Axial mode helical Antenna for NOAA-18 HRPT Reception at 1700MHz
  • Optimization of SDR Based Weather Satellite image  Reception
  • Dual Band Wearable Antenna for Communication and Navigation
  • Support Vector regression for the design of array antennas
  • Hardware Trojan Detection using scalable gate level characterization
  • VLSI Architecture for Video Watermarking During Compression
  • Design and implementation of a Low power Color Image Watermarking chip
  •  Statistical Static Timing Analysis Using Parallel Processing of Timing Graphs
  • Design of an Optimized Double Precision Floating Point Divider using Cache Memory and a Multiplier
  • Decomposition and Synthesis of XOR Based Logic Circuits for LUT Based FPGAs
  • Parallel Multiplier-Accumulator unit based on Vedic mathematics.
  • Design for trust based hardware security.
  • Scheduling for Real time operating system
  • Static and Dynamic path allocation of Robots.
     

PhD program and area of focus

  • Secured testing of VLSI Circuits
  • VLSI Testing and Security
  • Design for Security
  • Antenna Design & Optimization
  • Hardware Design for Trust
  • Security in Multi-core Architectures
  • RF CMOS Design of Low-noise Amplifier
  • Detection and Diagnosis of Malicious activity in Hardware.
  • Broadband Distributed Amplifier (1-100 GHz) in 65nm CMOS for 100 Gb network
  • Distributed LNA (UWB band in 65nm CMOS)
  • BF Fundamental Frequency Oscillator (90 GHz and higher frequency in 65nm CMOS)
  • Quadrature VCO (60 GHz band in 65nm CMOS)
  • Injection Locked Frequency Divider (60 GHz and below in 65nm CMOS) for PLL
  • Class E Power Amplifier for RF Communication (millimetre wave in 65nm CMOS)
     

Funded projects

Title of the Research proposal - Hardware Trojan Detection and Consistency based Diagnosis

Investigators Dr. Nirmala Devi M., Dr. Jayakumar M., Mohankumar N., Dr.Sethumadhavan M.

Funding Agency – DRDO-New Delhi - 2015

Indian patent number 269540 granted as on 27/10/2015 of Kalyan Bhattacharyya (single author) titled “Tunable Distributed Voltage Controlled Oscillator for Generating High Frequency Microwave Signals” in CMOS Technology.

Publications

  1. Karthigha Balamurugan,  Nirmala Devi M. and Jayakumar M., "Design of V-Band Low Noise Amplifier using Current Reuse Topologies", International Journal of Applied Engineering Research (Accepted for Publication), 2015.
  2. Ramesh Bhakthavatchalu and Nirmala Devi M., "Crypto Keys Based Secure Access Control for JTAG and Logic BIST Architecture," International Journal of Engineering and Technology, 7(3):973-984, 2015
  3. Ramesh Bhakthavatchalu, Kannan, S. K., and Nirmala Devi, M., "Verilog Design of Programmable JTAG Controller for Digital VLSI IC's," Indian Journal of Science and Technology, 8(17), 2015.
  4. R. Lavanya, N. Nagarajan and M. Nirmala Devi, “Computer aided diagnosis of breast cancer by hybrid fusion of ultrasound and mammogram features”, Springer Advances in Intelligent Computing and Systems (AISC) series, vol 325, pp. 403-409, 2015.
  5. Aakash Indoria, Varatharajan Varrun, Akshay, Murali Krishna Reddy, Tejaswi Sathyasai, Baskaran Anand, Nirmala M. Devi, “State Variable Filter Design using Improvised Particle Swarm Optimization Algorithm”, Springer Advances in Intelligent Computing and Systems (AISC) series, vol 325, pp. 71- 78, 2015.
  6. Darshna Siva, T. Sangavi, Sheena Mohan, Sukanya Desikan and M. Priyatharishini," Tongue Controlled Mouse Pointer: An Assistive Technology For The Disabled", International Journal of Applied Engineering Research, ISSN 0973-4562 Vol.10 No.9 , pp. 23945-23952 (2015).
  7. R. Bharath , G. ArunSabari, Dhinesh Ravi Krishna, ArunPrasathe, K. Harish, N. Mohankumar, M. Nirmala Devi, Malicious Circuit Detection for Improved Hardware Security, Security in Computing and Communications, Vol 536 of the series Communications in Computer and Information Science ,  Proceedings of Third International Symposium, SSCC 2015, Kochi, India, , 2015.pp 464-472,2015, India
  8. PremLal Paleri, Ramesh.S.R “Early Stage FPGA Architecture Development by Exploiting Dependence on Logic density”,  International Journal Of Applied Engineering Research, ISSN 0973-4562 Volume 10, Number 11 (2015) pp. 28889-28902,July 2015
  9. Ramesh S. R, Dr.R.Jayaparvathy “Probabilistic Activity Estimator and Timing Analysis for LUT Based Circuits” , International Journal Of Applied Engineering Research, ISSN  0973-4562 Volume 10, Number 13 (2015) pp 33238-33242,August 2015
  10. Karthick S, Dr. Valarmathy S, Prabhu E, “Low Power Systolic Array Based Digital Filter for DSP Applications,” The Scientific World Journal, Vol.2015, pp:1-6, January 2015.
  11. Jithin S, Prabhu E, “Parallel Multiplier-Accumulator Unit Based on Vedic Mathematics” ARPN Journal of Engineering and Applied Sciences, Vol.9 No.22, May 2015, Vol. 10 No.8pp:3608-3613.
  12. BobbalaMadhukar Reddy, Prabhu E, “An Efficient 16-Bit Carry Select Adder With Optimized Power and Delay,” International Journal of Applied Engineering Research, Vol.10 No.11, July 2015, pp:27909-27916.
  13. Vigneshu R I, Dinesh Udhayan R, Raghav S, Wilfred Thadeus P, Anguselvan S, Prabhu E, “Design and implementation of digital household energy meter with a flexible billing unit using FPGA ,” International Journal of Applied Engineering Research, Vol.10 No.11, July 2015, pp:28331-28340.
  14. Ramesh Bhakthavatchalu and Nirmala Devi M., "Deterministic Test Data Compression in Logic BIST," International Journal of Applied Engineering Research 10(3):7537-7551.
  15. R. Lavanya, N. Nagarajan, M. Nirmala Devi, "False Positive Reduction in Computer Aided Detection of Mammographic Masses Using Canonical Correlation Analysis", Journal of Theoretical and Applied Information Technology (E-ISSN 1817-3195 / ISSN 1992-8645), indexed in [SCOPUS, EBSCO, INSPEC], 2014.
  16. Sarathkrishna S., Karthigha Balamurugan,  Nirmala Devi M. and Jayakumar M., ”Design and Analysis of GaN HEMT based LNA with CPW Matching”, 11th International Conference on Wireless and Optical Communications Networks (WOCN 2014), India  on 11th  – 13th  September 2014.
  17. Ramesh Bhakthavatchalu, Sreeja Krishnan, Vineeth V and Nirmala Devi Manickam, “Deterministic Seed Selection and Pattern Reduction in Logic BIST”, 18th Int. Symposium on VLSI Design and Test, VDAT 2014, PSG College of Technology, Coimbatore, India, July1 6-18, 2014.
  18. Gokul P R, Prabhu E, Dr.Mangalam H, “Performance Comparison of Multipliers based on Square and Multiply and Montgomery Algorithms,” Proceedings of the IEEE International Conference on Green Computing, Communication and Electrical Engineering (ICGCCEE-2014), 6-8th March 2014, pp:465-469.
  19. Karunakaran, D.K., Mohankumar, N., Malicious combinational Hardware Trojan detection by Gate Level Characterization in 90nm technology, 5th International Conference on Computing Communication and Networking Technologies, ICCCNT 2014, China   
  20. Remy M, Prabhu E, Mangalam H, “A Versatile Low Power Design of Bit-Serial Multiplier in Finite Fields GF (2m),” Proceedings of the IEEE International Conference on Communication and Signal Processing (ICCSP 2014), April 3-5 2014, pp:474-478.
  21. Karthick S, Dr. Valarmathy S, Prabhu E, “Low Power Heterogeneous Adder ,” International Journal of Applied Engineering Research, Vol.9 No.22, 2014, pp:13449-13464.
  22. Anand, B., Aakash, I., Akshay, Varrun V., Reddy, M.K., Sathyasai T., Nirmala Devi M., “Improvisation of particle swarm optimization algorithm”, Int. Conf. on Signal Processing and Integrated Networks, SPIN 2014, Feb 20-21, 2014, Noida, Delhi-NCR, India, Proc. Published by IEEE, ISBN 978-1-4799-2865-1, pp. 20 –24.
  23. Mahalakshmi, B S., Manikantan S., Bhavana P., Prem Anand M., SaiEknaath Rss., Nirmala Devi M., “Small signal modelling of GaN HEMT at 70GHz”, Int. Conf. on Signal Processing and Integrated Networks, SPIN 2014, Feb 20-21, 2014, Noida, Delhi-NCR, India, Proc. Published by IEEE, ISBN 978-1-4799-2865-1, pp. 739 – 743.
  24. Janapati Sirisha, Nikkitha Vaishnavi V C, Nirmita K P, Shree Vidhya S, Yameni G , Karthigha Balamurugan,  Nirmala Devi M., Jayakumar M.,  “Study and Design of CMOS Based Millimeter Wave LNA Including Noise Models”, International Conference on Communication and Computing, ICC 2014, June 12-14, Bangalore, India, Proc. Published by Elsevier.
  25. Ramesh Bhakthavatchalu and Nirmala Devi.M., (2014), Reconfigurable Logic Built in Self-Test technique for SoC Applications, International Conference on Communication and Computing, ICC 2014, June 12-14, Bangalore, India, Proc. Published by Elsevier, (3):1-8.
  26. Padmapriya Sankar, and Nirmala Devi M, “Particle Swarm Optimization with Different Modifications”, Third Int. Conf on Recent Trends in Engg., & Tech, Chanwad, Proc. Published in Elsevier Science and Technology, pp. 551 – 556, 2014.
  27. G.Srujana, S. Radhika, S. Sonu, T. Vishwanth Sai, V. Tharun , M. Nirmala Devi, “Improved Particle Swarm Optimisation with Modified Velocity Calculation”, IEEE Workshop on Computational Intelligence: Theories, Applications and Future Directions, 14th July 2013, Indian Institute of Technology, (IIT) Kanpur, pp.108-113.
  28. Prabhu E, Dr. Mangalam.H, S.Karthick, “A low power multiplier using encoding and bypassing technique,” Journal of Theoretical and Applied Information Technology, Vol. 57 No.2, 20th November 2013, pp:252-260.
  29. S. Karthick, Dr. S. Valarmathy, E. Prabhu, “Reconfigurable FIR filter with radix-4 array multiplier,” Journal of Theoretical and Applied Information Technology, Vol. 57 No.3, 30th November 2013, pp:326-336. 
  30. D Abhilash, Akshaya Sankar, S Janakiraman, G Ravi Kiran,Roshni Kaur Sudan, and V   Mekaladevi, “Compressive Sensing for Pulse Position Modulated UWB Signal” AIM/CCPE 2012,Springer-Verlag Berlin Heidelberg 2012CCIS, 296, pp. 115–121, 2012.
  31. Sruthi.P.R and M.Nirmala Devi, “A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power", Sixteenth International Symposium on VLSI Design and Test (VDAT 2012), Bengal Engineering and Science University, Shibpur,Kolkata , India, July 1-4, 2012, published by Springer - Lecture Notes in Computer Science (LNCS volume number 7373), pp. 198-208, ISBN 978-3-642-31493-3, Scopus indexed.
  32. Sruthi.P.R and M.Nirmala Devi, “Modified AVR Code for Test Data Compression”, The 7th International Workshop on Unique Chips and Systems (UCAS-7), Feb. 26 in conjunction with The 18th International Symposium on High Performance Computer Architecture, IEEE Computer Society, New Orleans, Louisiana, USA, February 25-29, 2012.
  33. D.Badari Nath, Arun Scaria, M.Nirmala Devi and N.Mohankumar, “VLSI Architecture for Compressed Domain Video Watermarking”, the First International Workshop on Peer-to-Peer Networks and Trust Management, Chennai, India, July 15 ~ 17, 2011, published by Springer in Communications in Computer and Information Science (CCIS) Series, Scopus indexed.
  34. Mohankumar, N., Nirmala Devi, M., BadariNath, D., Scaria, A., VLSI architecture for compressed domain video watermarking, 2011Communications in Computer and Information Science CCIS,pp- 405,India
  35. Badarinath, D., Scaria, A., Devi, M.N., Mohankumar, N. A., Compressed domain dual video watermarking for real-time applications, Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011, India
  36. Scaria, A., BadariNath, D., Nirmala Devi, M., Mohankumar, N., Hardware implementation of svd based colour image watermarking in wavelet domain, Proceedings of 2011 International Conference on Process Automation, Control and Computing, PACC 2011,India
  37. M. Nirmala Devi and S. Arumugam, “VLSI Implementation of Artificial Neural Networks A survey”, ACTA Press International journal of Modelling and Simulation, Vol. 30, Issue 2, ISSN 1925-7082, EI compendex, Inspec index, Calgary, Canada, 2010.
  38. Sai Chand, Nirmala Devi M., Arumugam S., FPGA Realization of Activation Function for Artificial Neural Networks, IEEE Eighth International Conference on Intelligent System Design and Applications (ISDA 08), Taiwan, November 26-28, 2008, pp. 159-164.
  39. Mohankumar, N., Bhuvan, B., NirmalaDevi, M., Arumuga, S., A modified genetic algorithm for evolution of neural network in designing an evolutionary neuro-hardware, Proceedings of the International Conference on Genetic and Evolutionary Methods, GEM 2008, Lasvegas.
     

Laboratory facilities

  • VLSI Design Laboratory
  • Hardware Security Laboratory