Members

Major research objectives

The advancement in VLSI technology and its impact on the complexity of VLSI chips has made the testing of these chips very crucial. Thus testing plays a key role in the design flow and is therefore a challenging task for design and test engineers. The major research objectives are

  • Test pattern generation
  • Fault diagnosis and analysis
  • Low power VLSI
  • Reconfigurable computing
  • Test data compression
     

Selected projects by UG / PG students

  • n-detect Test pattern generation and relaxation using ZBDDs
  • Test power reduction and test pattern generation using PSO
  • Test power reduction and test pattern generation using ZBDDs
  • Multiple fault diagnosis of digital circuits using the optimal neural network model
  • Multiple fault diagnosis in VLSI circuits using Binary decision diagrams

PhD program and area of focus

VLSI Design, VLSI Testing, Low Power VLSI Design

Publications

  1. Navya Mohan, Anita J. P. , “A Zero Suppressed Binary Decision Diagram based test set relaxation for single and multiple stuck-at faults,” in the International Journal of Mathematical Modelling and Numerical Optimisation. (Accepted for publication)
  2. Sinduja  V.,  Raghav S.,  Anita J. P., "Efficient don't-care filling method to achieve reduction in test power”, Proc. International Conference on Advances in Computing, Communications and Informatics, ICACCI 2015.
  3. Deepak Rajan, J. P. Anita, “Static Relaxation Technique with Test Vector Compression”, in the International Journal of Applied Engineering Research, Vol.10, No.11, 2015.
  4. J. P. Anita, P. T. Vanathi, “Genetic Algorithm Based Test Pattern Generation for Multiple Stuck-at Faults and Test Power Reduction in VLSI Circuits”, Proc. International Conference on Electronics and Communication Systems (ICECS -2014), 2014.
  5. J. P. Anita, P. T. Vanathi, “Multiple Fault Diagnosis and Test Power Reduction Using Genetic Algorithms”, in Communications in Computer and Information Science, Vol.305, Springer-Verlag, Berlin Heidelberg, pg 84-92, 2012.
  6. Reeja Raju, J. P. Anita, P. T. Vanathi, “A Novel approach for Multiple arbitrary Fault diagnosis in Combinational circuits”, Proc. IEEE sponsored International conference on Process Automation Control and Computing, July’11.
  7. J. P. Anita, P. T. Vanathi,  “Multiple Fault diagnosis with improved diagnosis resolution for VLSI circuits”, Proc. IEEE sponsored International conference on Computing, Communication and Networking Technologies, July’10.
     

Opportunities for projects UG/ PG/ PhD

Research areas include Test pattern generation, Fault modeling, Fault analysis, Fault detection, Low power VLSI, Reconfigurable computing