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Course Detail

Course Name Electronic System Level Design and Verification
Course Code 15ECE365
Program B. Tech. in Electronics and Communication Engineering
Year Taught 2019


Unit 1

Electronic system level design: Languages (C++, Verilog and SystemC) – Flows and methodologies – Architecture exploration, Models for system level design and functional Simulation,

Unit 2

Electronic system level verification: Verification languages (Verilog and System Verilog) – Verification flows and methodologies (UVM) – HW-SW co-verification

Unit 3

Open source tools – Bluespec and Accellera, case study.

Text Books

  1. Michael D. Ciletti, “Advance Digital Design with Verilog HDL”, Pearson Higher Education, 2011.
  2. Chris Spear and Greg Tumbush, “System Verilog for Verification: A Guide to Learning the Testbench Language Features” Third Edition, Springer, 2012.


  1. Sandro Rigo, Rodolfo Azevedo and Luiz Santos, “Electronic System Level Design – An Open-Source Approach”, Springer, 2011.
  2. Brian Bailey and Grant Martin, “ESL Models and their Application for Electronic System Level Design and Verification in Practice”, Springer, 2010.
  3. David Black, Jack Donovan, Bill Bunton and Anna Keist, “System C from the ground up”, Second Edition, Springer, 2010.

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