COURSE SUMMARY
Course Title: 
RISC Processor Design using HDL
Course Code: 
15ECE370
Year Taught: 
2015
Type: 
Elective
Degree: 
Undergraduate (UG)
School: 
School of Engineering
Campus: 
Bengaluru
Chennai
Coimbatore
Amritapuri

'RISC Processor Design using HDL' is an elective course offered for the B. Tech. (Bachelor of Technology) in Electronics and Communication Engineering at School of Engineering, Amrita Vishwa Vidyapeetham.

Unit 1

Fundamental techniques of computer design: RISC and CISC architectures - Computer arithmetic - Comparison of RISC and CISC architectures. Verilog: Introduction and review of basic designs using verilog. MIPS processor: Introduction to MIPS features - MIPS instruction set - Logical design of MIPS data path - Control unit and instruction decoder.

Unit 2

Design of single cycle - Multicycle and pipelined architectures of MIPS. Introduction to superscalar - Super pipelined architectures - Performance evaluation of super scalar processors. Verilog design of a pipelined MIPS processor.

Unit 3

Introduction to memory hierarchy: Cache memory fundamentals - Memory systems for superscalar processors. Static timing analysis: Introduction - Setup and hold time constraints - Processor timing issues - Design examples.

  1. V.Carl Hamacher, Zvonko G. Vranesic and Safwat G. Zaky, "Computer Organisation", Fifth edition, McGraw-Hill Inc, 1996.
  2. Hennessy, John L. and David A. “Pattreson, Computer architecture: a quantitative approach”, Elsevier, 2012.
  3. Bhaskar J and Rakesh Chadha, “Static timing analysis for Nanometer designs”, Springer 2009.
  4. Dandamudi, Sivarama P, “Guide to RISC processor for programmers and engineers”, Springer, 2005
  5. Hayes, John P, “Introduction to digital logic design, Addison”, Wesley Longman publishing co., Inc, 1993.
  6. Bhasker, Jayaram, “A verilog HDL Primer”, Star galaxy publishing, 1999