Course

Module I

Issues in Digital Integrated Circuit Design – From Custom to Semicustom and Structured Array Design Approaches -MOSFETs as switches –Device characteristics – Non ideal I-V effects. NMOS and CMOS physical layouts and stick diagrams – Design Rules – Physical Design – NMOS and CMOS layers – Designing FET arrays – FET sizing and unit transistor – Physical design of logic gates and design hierarchies.

Module II

Analysis of MOS logic gates – DC switching characteristics of NMOS and CMOS inverters – DC characteristics of NAND and NOR gates – Transient response – Gate design for transient performance – Transmission gates and pass transistors.

Module III

Designing high speed CMOS logic networks – Gate delays – Driving large capacitive loads – BiCMOS drivers – Clocking and data flow control – Advanced techniques in CMOS logic circuits – Mirror circuits – Pseudo-NMOS – Tristate circuits – Clocked CMOS – Dynamic CMOS logic circuits-Static Latches and Registers- Dynamic Latches and Registers.

Course Objectives

• To develop understanding of MOSFETs and its characteristics to enable designing digital logic circuits
• Provides the fundamental knowledge to analyze static, transient and dynamic response of CMOS digital logic design
• Delivers a comprehensive foundation about CMOS physical design

Course Outcomes

• CO1: Able to understand and implement simple logic circuits using CMOS
• CO2: Able to analyze different CMOS gate realizations
• CO3: Able to understand and analyze performance trade-offs in CMOS VLSI systems
• CO4: Able to implement layouts of simple CMOS circuits

CO – PO Mapping

Textbook(s)

• J. P. Uyemura, “Introduction to VLSI Circuits and Systems”, John Wiley and Sons, Second Edition, 2002. Jan M. Rabey, Anantha Chandrakasan, and Borivoje Nikolic, “Digital Integrated Circuits-A Design Perspective”, Second Edition, Prentice Hall/Pearson, 2003.

Reference(s)

• Neil Weste, David Harris, Ayan Banerjee, “CMOS VLSI Design: A Circuits and Systems Perspective”, Pearson Education, 4^th Edition, 2011.
• Sung-Mo Kang, Yusuf Leblechi, “CMOS Digital Integrated Circuits – Analysis and Design”, Tata McGraw Hill Publishing Company Limited, Third Edition, 2003.

Evaluation Pattern