Unit 1
Introduction to Digital Signal Processing Systems – Iteration bound – Pipelining and Parallel Processing – Retiming – Unfolding – Folding.
| Course Name | VLSI Signal Processing Systems |
| Course Code | 15ECE372 |
| Program | B. Tech. in Electronics and Communication Engineering |
| Year Taught | 2019 |
Introduction to Digital Signal Processing Systems – Iteration bound – Pipelining and Parallel Processing – Retiming – Unfolding – Folding.
Systolic Architecture Design – Fast Convolution – Algorithmic Strength Reduction in Filters and Transforms – Pipelined and Parallel Recursive and Adaptive Filters.
Scaling and Round off Noise – Digital Lattice Filter Structures – Bit-Level Arithmetic Architectures – Redundant Arithmetic – Numerical Strength Reduction – Low- Power Design.
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