Introduction to verilog HDL: ASIC / FPGA design flow – Advantages of HDL – Overview of digital design with verilog HDL. Hierarchical modeling: Basic concepts – Modules and ports. Overview of different levels of abstractions: Gate level modeling – Dataflow modeling – Behavioral modeling – Switch level modeling.
Logic synthesis with verilog HDL: Impact of logic synthesis – Interpretation of a few verilog constructs – Synthesis design flow – Concepts of verification. Introduction to FPGA fabrics: FPGA architectures – SRAM-based FPGAs – Permanently programmed FPGAs – Circuit design of FPGA fabrics – Architecture of FPGA fabrics – Logic implementation of FPGAs – Physical design for FPGAs.
Architecture and large scale Systems: Behavioral design – Design methodologies – Buses – Platform FPGAs – Multi FPGA systems – Novel architecture – FPGA design cycle using Xilinx ISE webpack.