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Course Detail

Course Name VLSI System Design
Course Code 15ECE373
Program B. Tech. in Electronics and Communication Engineering
Year Taught 2019

Syllabus

Unit 1

Introduction to verilog HDL: ASIC / FPGA design flow – Advantages of HDL – Overview of digital design with verilog HDL. Hierarchical modeling: Basic concepts – Modules and ports. Overview of different levels of abstractions: Gate level modeling – Dataflow modeling – Behavioral modeling – Switch level modeling.

Unit 2

Logic synthesis with verilog HDL: Impact of logic synthesis – Interpretation of a few verilog constructs – Synthesis design flow – Concepts of verification. Introduction to FPGA fabrics: FPGA architectures – SRAM-based FPGAs – Permanently programmed FPGAs – Circuit design of FPGA fabrics – Architecture of FPGA fabrics – Logic implementation of FPGAs – Physical design for FPGAs.

Unit 3

Architecture and large scale Systems: Behavioral design – Design methodologies – Buses – Platform FPGAs – Multi FPGA systems – Novel architecture – FPGA design cycle using Xilinx ISE webpack.

Text Books

  1. Wayne Wolf, “FPGA-Based System Design”, First Edition, Prentice Hall India Private Limited, 2004.
  2. Samir Palnitkar, “Verilog HDL”, First Edition, Prentice Hall India Private Limited, 2003.

Resources

  1. tephen Brown, ZvonkoVranesic, “Fundamentals of Digital Logic with Verilog Design”, First Edition, Tata McGraw Hill Publishing Company Limited, 2002.
  2. Stephen M.Trimberger, “Field-Programmable Gate Array Technology”, Springer, 1994.
  3. Clive Maxfield, “The Design Warrior’s Guide to FPGAs”, Elsevier, 2000

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