COURSE SUMMARY
Course Title: 
VLSI System Design
Course Code: 
15ECE373
Year Taught: 
2015
Type: 
Elective
Degree: 
Undergraduate (UG)
School: 
School of Engineering
Campus: 
Bengaluru
Chennai
Coimbatore
Amritapuri

'VLSI System Design' is an elective course offered for the B. Tech. (Bachelor of Technology) in Electronics and Communication Engineering at School of Engineering, Amrita Vishwa Vidyapeetham.

Unit 1

Introduction to verilog HDL: ASIC / FPGA design flow – Advantages of HDL – Overview of digital design with verilog HDL. Hierarchical modeling: Basic concepts – Modules and ports. Overview of different levels of abstractions: Gate level modeling – Dataflow modeling – Behavioral modeling – Switch level modeling.

Unit 2

Logic synthesis with verilog HDL: Impact of logic synthesis – Interpretation of a few verilog constructs – Synthesis design flow – Concepts of verification. Introduction to FPGA fabrics: FPGA architectures – SRAM-based FPGAs – Permanently programmed FPGAs – Circuit design of FPGA fabrics – Architecture of FPGA fabrics – Logic implementation of FPGAs – Physical design for FPGAs.

Unit 3

Architecture and large scale Systems: Behavioral design – Design methodologies – Buses – Platform FPGAs – Multi FPGA systems – Novel architecture – FPGA design cycle using Xilinx ISE webpack.

TEXTBOOKS

  1. Wayne Wolf, “FPGA-Based System Design”, First Edition, Prentice Hall India Private Limited, 2004.
  2. Samir Palnitkar, “Verilog HDL”, First Edition, Prentice Hall India Private Limited, 2003.

REFERENCES

  1. Stephen Brown, ZvonkoVranesic, “Fundamentals of Digital Logic with Verilog Design”, First Edition, Tata McGraw Hill Publishing Company Limited, 2002.
  2. Stephen M.Trimberger, “Field-Programmable Gate Array Technology”, Springer, 1994.
  3. Clive Maxfield, “The Design Warrior’s Guide to FPGAs”, Elsevier, 2000