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Course Detail

Course Name VLSI System Design
Course Code 15ECE373
Program B. Tech. in Electrical and Electronics Engineering
Credits Campus: Bengaluru, Coimbatore, Amritapuri
Year Taught 2015
Year Taught 2016
Year Taught 2017
Year Taught 2018

Syllabus

Unit 1

Introduction to verilog HDL: ASIC / FPGA design flow – Advantages of HDL – Overview of digital design with verilog HDL. Hierarchical modeling: Basic concepts – Modules and ports. Overview of different levels of abstractions: Gate level modeling – Dataflow modeling – Behavioral modeling – Switch level modeling.

Unit 2

Logic synthesis with verilog HDL: Impact of logic synthesis – Interpretation of a few verilog constructs – Synthesis design flow – Concepts of verification. Introduction to FPGA fabrics: FPGA architectures – SRAM-based FPGAs – Permanently programmed FPGAs – Circuit design of FPGA fabrics – Architecture of FPGA fabrics – Logic implementation of FPGAs – Physical design for FPGAs.

Unit 3

Architecture and large scale Systems: Behavioral design – Design methodologies – Buses – Platform FPGAs – Multi FPGA systems – Novel architecture – FPGA design cycle using Xilinx ISE webpack.

Text Books

  • Wayne Wolf, “FPGA-Based System Design”, First Edition, Prentice Hall India Private Limited, 2004.
  • Samir Palnitkar, “Verilog HDL”, First Edition, Prentice Hall India Private Limited, 2003.

References

  • Stephen Brown, Zvonko Vranesic, “Fundamentals of Digital Logic with Verilog Design”, First Edition, Tata McGraw Hill Publishing Company Limited, 2002.
  • Stephen M. Trimberger, “Field-Programmable Gate Array Technology”, Springer, 1994.
  • Clive Maxfield, “The Design Warrior’s Guide to FPGAs”, Elsevier, 2000.

‘VLSI System Design’ is a course offered in B. Tech. in Electrical and Electronics Engineering program at School of Engineering, Amrita Vishwa Vidyapeetham.

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