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Dr. Ramesh S. R.

Assistant Professor, Electronics and Communication Engineering, School of Engineering, Coimbatore

Qualification: M.E, Ph.D
sr_ramesh@cb.amrita.edu
Ph: +91- 9894391731, +91 422 2685000 Ext. 5731
Ramesh S. R's Google Scholar Profile

Bio Publications Education Professional Experience Academic Responsibilities Undergraduate Courses Handled Post-Graduate / Ph.D. Courses Handled Participation in Faculty Development / STTP / Workshops /Conferences Organizing Faculty Development / STTP / Workshops /Conferences Academic Research – PG Projects Research Expertise PG Projects UG Projects Teaching
Bio

Dr. Ramesh S. R. currently serves as an Assistant Professor (Senior Grade) in the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Coimbatore Campus. He joined Amrita in July 2007. He completed his Ph.D. in Static Timing Analysis from Anna University, Chennai in 2020 and Master of Engineering in VLSI Design from Arulmigu Kalasalingam College of Engineering (Anna University, Chennai ) in 2007. He did his Bachelor of Engineering in ECE from Cape Institute of Technology (Anna University, Chennai) in 2005. His areas of interest include Static Timing analysis, Hardware Trojan Detection, VLSI CAD, FPGA Logic Architectures, Low power VLSI, IOT and Embedded Sensor Networks. He is an Associate Member in IETE. He is a reviewer for many reputed International Journals. He serves as a Doctoral Committee member for various students.

Publications
Education
  • Ph. D. in VLSI
    Anna University, Chennai
  • 2007: M. E. in VLSI
    Anna University, Chennai/ Arulmigu Kalasalingam College of Engineering
Professional Experience
Year Affiliation
July 2011 to Present Assistant Professor (Sr. Gr), Amrita Vishwa Vidyapeetham
Domain: Teaching, Research
July 2009 to June 2011 Assistant Professor, Amrita Vishwa Vidyapeetham
Domain: Teaching, Research
July 2007 to June 2009 Lecturer, Amrita Vishwa Vidyapeetham
Domain: Teaching
Academic Responsibilities
SNo Position Class / Batch Responsibility
1. Batch Coordinator 2015-19 Coordinating class Advisers for smooth conduct of academics
2. Class Adviser 2015 – 19 EIE Monitoring Students and counseling
3. Mentor Open Lab 2017-18 Third Year ECE and EIE Facilitates hardware prototyping and arrangement of resources
4. Project Coordinator 2018-19 Final Year ECE and EIE Coordinating class Advisers for conduct of project reviews
Undergraduate Courses Handled
  1. CMOS Integrated Circuits
  2. Electronics Engineering
  3. Electronic Circuits
  4. VLSI Design
  5. VLSI Technology
  6. Linear Integrated Circuits
Post-Graduate / Ph.D. Courses Handled
  1. Solid State Devices (VLSI Design)
  2. CAD for VLSI (VLSI Design)
  3. Micro Electromechanical Systems (VLSI Design)
  4. Static Timing Analysis (VLSI Design)
  5. Analysis and Design of Mixed Signal VLSI Circuits (VLSI Design)
  6. VLSI Fabrication Technology (VLSI Design)
Participation in Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. Author Workshop on “scholarly writing and publishing” ASE, Ettimadai April 11, 2018 Research
2. ISTE STTP on CMOS, Mixed Signal and Radio Frequency VLSI Design IIT Kharagpur January 30 – February 4, 2017 Course Plan development for PG
3. National workshop on Signal and Image processing Applications using Xilinx system generator ASE,Ettimadai April 10 – 11, 2014 Research
4. Research Seminar on Emerging Perspectives in Nanoelectronics R&D ASE, Ettimadai September 19, 2014  Research
5. ISTE workshop on Analog Electronics IIT Kharagpur June 4 -14, 2013 PG Elective course
6. Workshop on Research and Project Areas in VLSI Design ASE, Ettimadai January 25, 2013 Research
7. ISTE workshop on Writing Effective Conference Papers IIT Bombay February 18 – 19, 2012 Research
8. Mission 10X workshop ASE & Wipro December 20 – 24, 2010 Innovative Teaching
9. Pre-Conference workshop on Embedded Systems Coimbatore Institute of Technology July 13, 2010 Research
10. Course on Nanotechnology ASE, Ettimadai July 13, 2009 Research
11. Workshop on UltraSparc T2 Processor microarchitecture Sun Microsystems March 29 – 30, 2008 Research
12. Workshop on Optical Communication and Network Design and Modeling Coimbatore Institute of Technology February 4, 2008 Research
Organizing Faculty Development / STTP / Workshops /Conferences
SNo Title Organization Period Outcome
1. National Conference on Recent Trends in Communication and Signal Processing RTCSP’09 ASE, Ettimadai April 7, 2009 Research
2. Student Project Contest ASE, Ettimadai February 29, 2008 Practical knowledge and Innovation
Academic Research – PG Projects
SNo Name of the Scholar Program Specialization Duration Status
1. Akella Krishna Vamsi VLSI Design Low Power VLSI 2018-19 Ongoing
2. LachiReddy Dhanunjay VLSI Design Low Power VLSI 2018-19 Ongoing
3. Nithya J VLSI Design Low Power VLSI 2018-19 Ongoing
4. Kosanam Manikanth VLSI Design Static Timing Analysis 2017-18 Completed
5. Mukkamala Venkata Durga Pavan VLSI Design Low Power VLSI 2017-18 Completed
6. Sreenath K VLSI Design Static Timing Analysis 2016-17 Completed
7. Haritha H VLSI Design Low Power VLSI 2016-17 Completed
8. Samarshekar R VLSI Design Static Timing Analysis 2015-16 Completed
9. Prem Lal Paleri VLSI Design VLSI CAD 2014-15 Completed
Research Expertise
  • As of July 2021 the number of students working at various levels under his supervision are:
    • M.Tech – 3 (Static Timing Analysis and Hardware Trojan Detection)
    • B.Tech – 2 (IOT, VLSI)
PG Projects
  • A MUX based Latch Technique for Hardware Trojan Detection
  • Hardware Trojan Detection using Ring Oscillator
  • Flip Flop Based Approach for Logic Encryption Techniques
  • An Approach for Statistical Parameter Estimation and Test pattern Generation
  • Power and Area Efficient Booth Multiplier
  • MAC Unit design and its impact on a Trained Neural Network
  • Hybrid Adder Design for High Speed Applications
  • Power and Delay Efficient ALU using Vedic Techniques
  • An Efficient Booth Multiplier using Probabilistic Approach
  • An Efficient Linear Pipeline Circuit with Optimal Power Delay Product using Soft Edge Flip flops
  • Analytical Modeling of Logic Resource Utilization for Early Stage FPGA Architecture Development
  • Statistical Static Timing Analysis Using Parallel Processing of Timing  Graphs
  • Design And Implementation of 1D Discrete Multiwavelet Transform For Infrasound Classification
  • Statistical Timing Analysis Using Probabilistic Approaches
  • Decomposition And Synthesis of XOR Based Logic Circuits For LUT Based FPGAs
  • Probabilistic Activity Estimator For4-input LUT Based FPGA Circuits
  • Data Flow Transformation for Optimization of Digital/DSP Circuits
  • Design of an Optimized Double Precision Floating Point Divider Using Cache Memory and a Multiplier
  • FPGA Implementation of Low Density Parity Check Code Decoder
UG Projects
  • FPGA Implementation of Power and Area Efficient 32 bit MAC Unit
  • A Signed Vedic Multiplier using Redundant Binary Representation
  • Hardware Trojan Detection using Supervised Machine Learning
  • Development of a System to measure Hemoglobin non-invasively
  • Low Delay VLSI Architecture Design for Logarithmic Multiplication
  • A Low Power Cubic Computation Unit using Vedic Techniques
  • Design of Low power Binary Square rooter using Reversible Logic
  • Design of Power Efficient Approximate Multipliers
  • FPGA Implementation of Low power LNS Arithmetic Unit by LUT Partitioning
  • A Comparative analysis on Static and Statistical Timing Techniques
  • An Efficient FIR Filter Design Using Common Sub Expression Elimination Method
  • Multimode Floating Point Adder and Multiplier
  • Power Estimation of Combinational Circuits Using Spatial Correlation
Teaching
  • Electronic Circuits
  • VLSI Technology
  • Digital IC Design
  • VLSI Design
  • VLSI System Design
  • Linear Integrated Circuits
  • Static Timing Analysis
  • Solid State Devices
  • Semiconductor Memory Design
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