Publication Type : Conference Paper
Publisher : 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), IEEE
Source : 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), IEEE, Abu Dhabi, United Arab Emirates, p.1–4 (2016)
Url : https://ieeexplore.ieee.org/abstract/document/7870034
Keywords : clock gating technique, Clock gating techniques, clock signals, Clocks, D Flip Flop, D Latch, d-flip flop, Dynamic Power, flip-flops, gating logic, hold phase, Latches, leakage control transistor, LECTOR, Logic gates, low power flip flop application, nanoelectronic circuit design, nanoelectronics, portable battery-powered electronics device, Power dissipation, PTM technology, sequential circuit elements, sequential circuits, short circuit power, size 32 nm, size 45 nm, size 65 nm, size 90 nm, Static & Dynamic Power, Static Power, Switches, Transistors, voltage 1.1 V
Campus : Amritapuri
School : Department of Computer Science and Engineering, School of Engineering
Department : Computer Science
Year : 2016
Abstract : The continuous growing demand of portable battery-powered electronics devices hunts for Nano-electronic circuit design for ultra-low power applications by reducing dynamic power, static power and short circuit power. In sequential circuit elements of an IC, a notable amount of power dissipation occurs due to the rapid switching of high frequency clock signals, which do not fetch any data bit or information. The needless switching of clock, during the HOLD phase of either `logic 1' or `logic 0', may be abolished using gated clock. In this paper, we have presented a new clock gating technique incorporating Leakage Control Transistor. The improvised technique is employed to trigger a D-Flip Flop using 90nm PTM technology at 1.1V power supply. We have observed an impressive reduction in power, delay and latency using the proposed gating logic, which has outsmarted the existing works. The simulation is also performed in smaller technology nodes such as 65nm, 45nm and 32 nm to notice the change in delay, dynamic power and static power of the circuit.
Cite this Research Publication : Dr. Pritam Bhattacharjee, Alak Majumder, and Tushar Dhabal Das, “A 90 nm leakage control transistor based clock gating for low power flip flop applications”, in 2016 IEEE 59th International Midwest Symposium on Circuits and Systems (MWSCAS) (Scopus), Abu Dhabi, United Arab Emirates, 2016, pp. 1–4.