Publications

Abstract : The revolutions made in the CMOS technology are brought up by, continuous downscaling in order to obtain higher density, better performance and low power consumption, causing deleterious Short Channel Effects. Planar MOSFET’s have faced very hard challenges in the nanometer space, when ever the channel 4length happens to be in the same order of magnitude like the depletion-layer widths of drain and the source junctions. Hence, the channel length of the MOSFET’s should be great enough when compared to the sum of drain and source depletion widths in order to eradicate edge effects. Orelse numerous effects would occur. In MOSFET’s as channel Length diminishes the gate loose’s its control on the channel, as it isn’t good from power consumption point of view. MOSFET’s cannot control leakage path, removing leakage current is a path for improvising electrostatic control. A way of achieving it can be done by using a structure with multiple-gates as they allow the scaling of a transistor beyond the MOSFET scaling limit. In this case, the leakage current happens to be in the channel centre and reducing the channel decreases the current. Hence SOI and FINFET structures are used in order to achieve high gate-to-channel capacitance and decreases drain-to-channel capacitance. Another way of improvising the computational power can be done through changing the materials employed during manufacturing. In short, FINFET devices display superior SCE’s behaviour have considerably lower switching times, and higher current density than MOSFET technology. The review has been done on the various structures for performance escalation materials for FINFET structure performance Escalation as well as the various applications in which FINFET’s are used along with the various applications in which FINFET are used, various parameters used to perform RF and Linearity applications are noted.