Publication Type : Conference Paper
Publisher : International Conference on Advances in Engineering and Technology ICAET-2011, 2011
Source : International Conference on Advances in Engineering and Technology ICAET-2011, 2011
Campus : Chennai
School : School of Engineering
Center : Amrita Innovation & Research
Department : Electronics and Communication
Verified : Yes
Year : 2011
Abstract : Signal Integrity (SI) testing is the main issues in high speed ICs. Nowadays to test signal integrity in high speed ICs we need external probing and waveform monitoring at the gigahertz range which is not possible as the result we go for in-built monitors. This paper presents on chip testing for signal integrity. There are two monitors one is high level monitor which determines undershoots and the next is low level monitor which determines signal overshoots. These two monitors which traces the digital interconnect signals and determines the occurrences of undershoots and overshoots in the circuits. The working of these two monitors are been tested in an application oriented by connecting them with a D-Flip Flop. In further as the result of addition of these two monitors in a circuit the power consumption will be more so in order to reduce the power Multi-Threshold Complementary Metal Oxide Semiconductor (MTCMOS) circuit is been used here. The simulated results are been obtained which is been found to satisfy all theoretical concepts.
Cite this Research Publication : C. Ganesh Kumar, “A Multi-Threshold CMOS Technique in Built-In High-Speed Sensor for Digital Interconnect Signals”, International Conference on Advances in Engineering and Technology ICAET-2011, 2011.