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A Novel Low Voltage Hybrid Phase Locked Loop

Publisher : 2017 IEEE International Conference on Computational Intelligence and Computing Research, ICCIC 2017

Year : 2018

Abstract : pWith the trending growth in the VLSI industry, a low voltage design has become very important factor of any system. So optimizing the design for low voltage and high performance is a very subtle task. Keeping this in mind the work leads to a novel low voltage, high-performance hybrid Phase Locked Loop. The use of a Non-linear Phase Frequency Detector reduces the blind zone and dead zone regions. The use of simple Charge Pump with help of transmission gates for fast switching, and use of current starved VCO helps it to work at a very low voltage, the design optimization of the PFD and the Loop Filter adds to the performance and stability to the PLL. © 2017 IEEE./p

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