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A Survey on High-Throughput Non-Binary LDPC Decoders: ASIC, FPGA and GPU Architectures

Publication Type : Journal Article

Publisher : IEEE Communications Surveys & Tutorials

Source : IEEE Communications Surveys & Tutorials

Url :

Campus : Bengaluru

School : Department of Electronics and Communication Engineering

Verified : No

Year : 2021

Abstract : Non-binary low-density parity-check ( nbldpc) codes show higher error-correcting performance than binary codes when the codeword length is moderate and/or the channel has bursts of errors. The need for high-speed decoders for future digital communications led to the investigation of optimized nbldpc decoding algorithms and efficient implementations that target high throughput and low energy consumption levels. We carried out a comprehensive survey of existing nbldpc decoding hardware that targets the optimization of these parameters. Even though existing nbldpc decoders are optimized with respect to computational complexity and memory requirements, they still lag behind their binary counterparts in terms of throughput, power and area optimization. This study contributes to an overall understanding of the state-of-the-art on, and based systems, and highlights the current challenges that still have to be overcome on the path to more efficient nbldpc decoder architectures.

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