Publications

Abstract : The design of active delay circuits and variable delay elements is being investigated over the years as they are popular inside the integrated circuit chip, for example in on-chip clock distribution. The function of these kinds of circuit is to transfer the input signal at the output with an added amount of timing delay. For clock signals, it is important to achieve equal rise/fall time in order to support correct level-triggered-based on-chip sequential operation. However, most of the variable delay elements are unable to impart the matching of output rise/fall time. Therefore, in this article, we have unearthed a delay circuit which is expected to generate nearly equal rise/fall time at the output having a unique setup of delivering variable delay. A small-signal model for this proposed circuit is presented to note the related parameters for achieving the near-symmetric output rise/fall time. The circuit has been simulated in Cadence Virtuoso$$^{\textregistered }$$®for 90 nm Process Design Kit with an input signal of 1 GHz at 1.1 V power supply $$(V_{\mathrm{dd}})$$(Vdd). The simulation results assure that the expected functionality of our proposed variable delay architecture is sustained under different corner variations.