Publication Type : Conference Paper
Publisher : RVS College of Engineering and Technology
Source : Third International Conference on Intelligent Information Systems and Management(IISM), RVS College of Engineering and Technology, Coimbatore, 2012.
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2012
Abstract :
Cite this Research Publication : Ramesh S. R. and P.V, A., “Area and speed aware Decomposition of Logic circuits for Look Up Table based FPGAs”, in Third International Conference on Intelligent Information Systems and Management(IISM), RVS College of Engineering and Technology, Coimbatore, 2012.