Publications

Abstract : Complex numbers play a unique and very important role in many electrical engineering applications. Complex Binary Number System (CBNS) represents a given complex number as a single-unit binary string in contrast to x+iy form of representation using two real values usually represented in IEEE-754 format. Researchers have been exploring various hardware techniques for performing arithmetic operations on CBNS numbers. However, the existing CBNS hardware implementations suffer from the area, speed, and power overheads, with increasing data width. This work proposes an FPGA implementation of a CBNS Co-Processor which consists of an Arithmetic Unit (AU) that can add and subtract (-1+j)-base CBNS numbers of any data width, processing two-bits at a time. The proposed CBNS Co-Processor architecture is implemented on various FGPA platforms and verified its functionality. The proposed CBNS Co-Processor executes addition and subtraction operations 2.36 and 3.22 times faster respectively compared to the existing CBNS adder and subtractor implementations.