Publications

Abstract : In this work, a high throughput architecture for 1-D Discrete Wavelet Transform is proposed. The work proposes DWT computation through convolution of a `M' point input sequence with a `L' tap wavelet coefficients. Computation of DWT of an N point sequence is carried out by summing the results of blocks of `M' points. For illustration, an 8 tap filter and block size of 4 is considered. Through poly-phase filter structure and simple processing elements, effective computation is achieved. Architecture is 100% efficient in terms of hardware utilization and has an improved throughput of two fold. Xilinx ISE tools are used to carry out functional simulation and implementation. The proposed architecture can work at a maximum frequency of 398.25MHz while implementing on Virtex4 xc4vlx15-10sf363 target device.